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? 2006 microchip technology inc. advance information ds39776a mrf24j40 data sheet ieee 802.15.4? 2.4 ghz rf transceiver
ds39776a-page ii advance information ? 2006 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2006 microchip technology inc. advance information ds39776a-page 1 mrf24j40 devices included: ?mrf24j40 features: ? complete ieee 802.15.4 specification compliant ? supports miwi?, zigbee? and proprietary protocols ? simple, 4-wire spi interface ? integrated 20 mhz and 32.768 khz oscillator drive ? 20 mhz reference clock output: - available to drive microcontroller oscillator ? supports power-saving mode ? low-current consumption, typical 18 ma in rx mode and 22 ma in tx mode ? typical 2 a sleep mode ? small, 40-pin leadless qfn 6x6 mm 2 package rf/analog features: ? ism band 2.405-2.48 ghz operation ? -91 dbm typical sensitivity and +5 dbm maximum input level ? +0 dbm typical output power and 38.75 db tx power control range ? differential rf input/output and integrated tx/rx switch ? integrated low phase noise vco, frequency synthesizer and pll loop filter ? digital vco and filter calibration ? integrated rssi adc and i/q dacs ? integrated ldo ? high receiver and rssi dynamic range mac/baseband features: ? hardware csma-ca mechanism, automatic ack response and fcs check ? independent beacon, transmit and gts fifo ? hardware security engine (aes-128) with ctr, ccm and cbc-mac modes ? supports all cca modes and rss/lqi ? automatic packet retransmit capability ? supports in-line or stand-alone modes for both encryption and decryption pin diagram: 40-pin qfn 2 3 4 5 6 1 7 v dd rfp rfn v dd v dd gnd gpio0 mrf24j40 8 9 gpio1 gpio5 10 gpio4 12 13 14 15 16 11 17 gpio2 gpio3 reset gnd wake int sdo 18 19 sdi sck 20 cs 29 28 27 26 25 30 24 rxqp rxip lposc1 lposc2 clkout gnd gnd 23 22 nc gnd 21 v dd 32 33 34 35 36 31 37 v dd v dd osc2 osc1 v dd gnd v dd 38 39 nc v dd 40 lcap note: backside center pad is gnd. ieee 802.15.4 ? 2.4 ghz rf transceiver
mrf24j40 ds39776a-page 2 advance information ? 2006 microchip technology inc. table of contents 1.0 overview .................................................................................................................... .................................................................. 3 2.0 external connections ........................................................................................................ ........................................................... 7 3.0 memory organization ......................................................................................................... .......................................................... 9 4.0 serial peripheral interface (spi)........................................................................................... ...................................................... 13 5.0 ieee 802.15.4?-2003 ......................................................................................................... ...................................................... 19 6.0 initialization.............................................................................................................. ................................................................... 21 7.0 transmitting and receiving packets .......................................................................................... ................................................ 29 8.0 interrupts .................................................................................................................. .................................................................. 35 9.0 general purpose i/o ......................................................................................................... ......................................................... 39 10.0 electrical characteristics ................................................................................................. ........................................................... 41 11.0 packaging information...................................................................................................... .......................................................... 45 appendix a: layout and part selection.......................................................................................... ...................................................... 47 appendix b: mrf24j40 schematic and bill of materials ........................................................................... .......................................... 55 index .......................................................................................................................... .......................................................................... 59 the microchip web site ......................................................................................................... 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? 2006 microchip technology inc. advance information ds39776a-page 3 mrf24j40 1.0 overview the mrf24j40 is an ieee 802.15.4-2003 compliant transceiver supporting miwi ?, zigbee? and other pro- prietary protocols. the mrf24j40 integrates wireless rf, phy layer baseband and mac layer architectures that can be combined with a simple microprocessor to apply low data rate to a multitude of applications that include home automation, consumer electronics, pc peripherals, toys, industrial automation and more. the mrf24j40 device integrates a receiver, transmitter, vco and pll into a single integrated circuit. it uses advanced radio architecture to minimize external part count and power consumption. the mrf24j40 mac/baseband provides hardware architecture for both ieee 802.15.4 mac and phy layers. it mainly consists of tx/rx fifos, a csma-ca controller, superframe constructor, receive frame filter, security engine and digital signal processing module. the mrf24j40 is fabricated by advanced 0.18 m cmos process and is offered in a 40-pin qfn 6x6 mm 2 package. features are summarized in table 1-1 and the pinout for this device is listed in table 1-2. the mrf24j40 consists of four major functional blocks: 1. an spi interface that serves as a communica- tion channel between the host controller and the mrf24j40. 2. control registers which are used to control and monitor the mrf24j40. 3. the mac (medium access control) module that implements ieee 802.3? compliant mac logic. 4. the phy (physical layer) driver that encodes and decodes the analog data. the device also contains other support blocks, such as the on-chip voltage regulator, security module and system control logic. table 1-1: device features for the mrf24j40 (40-pin device) features mrf24j40 ieee 802.15.4? specification compliant yes integrated oscillator drive 20 mhz and 32.768 khz reference clock output 20 mhz power-saving mode support yes current consumption typical 18 ma in rx and 22 ma in tx sleep mode 2 a typical serial communications spi (4-wire) packages 40-pin leadless qfn 6x6 mm 2
mrf24j40 ds39776a-page 4 advance information ? 2006 microchip technology inc. figure 1-1: mrf24j40 architecture block diagram physical layer driver zigbee? protocol interrupt security spi interface mrf24j40 user application or miwi? protocol or proprietary protocol tx fifos long control registers short control registers rx fifo module rx mac reset rx phy tx phy tx mac
? 2006 microchip technology inc. advance information ds39776a-page 5 mrf24j40 1.1 pin descriptions table 1-2: mrf24j40 pin descriptions pin symbol type description 1v dd power rf power supply. bypass with a capacitor as close to the pin as possible. 2 rfp aio differential rf input/output (+). 3 rfn aio differential rf input/output (-). 4v dd power rf power supply. bypass with a capacitor as close to the pin as possible. 5v dd power guard ring power supply. bypass with a capacitor as close to the pin as possible. 6 gnd ground guard ring ground. 7 gpio0 dio general purpose digital i/o, also used as external pa enable. 8 gpio1 dio general purpose digital i/o, also used as external tx/rx switch control. 9 gpio5 dio general purpose digital i/o. 10 gpio4 dio general purpose digital i/o. 11 gpio2 dio general purpose digital i/o, also used as external tx/rx switch control. 12 gpio3 dio general purpose digital i/o. 13 reset di global hardware reset pin active-low. 14 gnd ground ground for digital circuit. 15 wake di external wake-up trigger. 16 int do interrupt pin to microcontroller. 17 sdo dio serial interface data output from mrf24j40. 18 sdi dio serial interface data input to mrf24j40. 19 sck di serial interface clock. 20 cs di serial interface enable. 21 v dd power digital circuit power supply. bypass with a capacitor as close to the pin as possible. 22 gnd ground ground for digital circuit. 23 nc ? no connection, do not connect anything to this pin. 24 gnd ground ground for digital circuit. 25 gnd ground ground for digital circuit. 26 clkout dio 20/10/5/2.5 mhz clock output. 27 lposc2 ai 32 khz crystal input (-). 28 lposc1 ai 32 khz crystal input (+). 29 rxip ao analog rx i channel output (+). 30 rxqp ao analog rx q channel output (+). 31 v dd power power supply for band gap reference circuit. bypass with a capacitor as close to the pin as possible. 32 v dd power power supply for analog circuit. bypass with a capacitor as close to the pin as possible. 33 osc2 ai 20 mhz crystal input (-). 34 osc1 ai 20 mhz crystal input (+). 35 v dd power pll power supply. bypass with a capacitor as close to the pin as possible. 36 gnd ground ground for pll. 37 v dd power charge pump power supply. bypass with a capacitor as close to the pin as possible. 38 nc ? no connection. 39 v dd power vco supply. bypass with a capacitor as close to the pin as possible. 40 lcap ? pll loop filter external capacitor. connected to external 180 pf capacitor. legend: a = analog, d = digital, i = input, o = output
mrf24j40 ds39776a-page 6 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 7 mrf24j40 2.0 external connections 2.1 oscillator the mrf24j40 is designed to operate at 20 mhz with a crystal connected to the osc1 and osc2 pins. a typical oscillator circuit is shown in figure 2-1. figure 2-1: crystal oscillator operation 2.2 oscillator start-up the mrf24j40 phy has an internal pll that must lock before the device is capable of transmitting or receiving packets. after a full power-on reset, the device requires 2 ms to lock. during this delay, all registers and buffer memory may still be read and written to through the spi bus. however, software should not attempt to transmit any packets (set the txrts (txnmtrig<0>)), or access any mac or phy registers during this period. 2.3 clkout pin the clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. the clkout has an inter- nal prescaler which can divide the output by 1, 2, 4 or 8. the clkout function is enabled via the clkctrl register (register 2-1) and the prescaler is selected via the rfctrl7 register (register 2-2). note 1: a series resistor (r s ) may be required for at strip cut crystals. c1 c2 xtal osc2 osc1 logic mrf24j40 r s (1) to internal register 2-1: clkctrl: divided sleep clock (50 khz) selection register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r ? clkoen sclkdiv<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 reserved: maintain as ? 0 ? bit 6 unimplemented: read as ? 0 ? bit 5 clkoen : 20 mhz clock output enable bit 1 = disable 0 = enable bit 4-0 sclkdiv4:sclkdiv0: divided slpclk selection bits divided by 2 n .
mrf24j40 ds39776a-page 8 advance information ? 2006 microchip technology inc. to create a clean clock signal, the clkout pin is held low for a period when power is first applied. after the power-on reset ends, the oscillator start-up timer (ost) will begin counting. when the ost expires, the clkout pin will begin outputting its default frequency of 2.5 mhz (main clock divided by 8). 2.4 rf output rfp and rfn are the differential rf input/output pins. these pins are connected to the antenna of the system, as seen in the example circuit diagram in figure a-1. l5 is an rf choke. this inductor filters out non 2.4 ghz voltages. l3, l4, c37 and c43 act as a balun. the balun converts a differential unbalanced input and converts it to a balanced singled-ended output and visa versa. l1, c23 and c38 form a pi-type matching circuit to match the impedance of the balun to the impedance of the antenna. this circuit is not required if the impedance of the balun matches the antenna impedance. refer to appendix a.1 ?layout considerations and rf measurements? for more details about board layout and part selection concerning the rf output pins. register 2-2: rfctrl7: rf control register 7 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 slpclk<7:6> ? ? ? ? clkdiv<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 slpclk7:slpclk6: sleep clock selection bits 00 = none 01 = external crystal 10 = internal ring oscillator 11 = reserved bit 5-2 unimplemented: read as ? 0 ? bit 1-0 clkdiv1:clkdiv0: mrf24j40 clock output frequency bits 00 = 2.5 mhz 01 = 5 mhz 10 = 10 mhz 11 = 20 mhz
? 2006 microchip technology inc. advance information ds39776a-page 9 mrf24j40 3.0 memory organization all memory in the mrf24j40 is implemented as static ram. there are five types of memory in the mrf24j40: ? short address control registers ? long address control registers ? transmit buffers ? receive buffers ? security buffer the control registers, both long and short, are used for configuration, control, and status retrieval of the mrf24j40. the control registers are directly read and written to by the spi interface. the transmit and receive buffers contain transmit and receive memory used by the controller to transmit and receive data. the security buffer provides an engine for the mrf24j40 mac, which is compatible with the ieee 802.15.4 lr-wpan (zigbee). the security buffer contains the following features: ? transmit encryption and receive decryption. ? seven-mode security suite. ? 64 x 8-bit security ram for security suite storing; one receive key and three transmit keys for tx fifos. beacon fifo and gts2 fifo share the same key space since they will not conflict with each other. normal fifo and gts1 fifo both have their own transmit key. ? security of apl and nwk layers can be achieved using the same engine. the upper layer security function is compliant to the zigbee v1.0 and zigbee 2006 specifications. the spi interface used to write and read these regis- ters is described in section 4.0 ?serial peripheral interface (spi)? . figure 3-1 shows the data memory organization for the mrf24j40. figure 3-1: mrf24j40 memory space short address control registers txb fifo long address control registers security buffer rx fifo txn fifo gts1 fifo gts2 fifo transmit buffers control registers security receive fifo 000h 07fh 080h 0ffh 100h 17fh 180h 1ffh 27fh 200h 280h 2beh 300h 38fh long address short address space 00h 3fh unimplemented 2bfh 2ffh space
mrf24j40 ds39776a-page 10 advance information ? 2006 microchip technology inc. 3.1 control registers the control registers provide the main interface between the host controller and the on-chip rf controller logic. writing to these registers controls the operation of the interface, while reading the registers allows the host controller to monitor operations. the control register memory is partitioned into the short address control register section and the long address control register section. all reserved registers may be read but their contents must not be changed. when reading and writing to registers which contain reserved bits, any rules stated in the register definition should be observed. figure 3-2: mrf24j40 short address control register mapping figure 3-3: mrf24j40 long address control register mapping rxmcr 00h panidl 01h panidh 02h sadrl 03h sadrh 04h eadr0 05h eadr1 06h eadr2 07h eadr3 08h eadr4 09h eadr5 0ah eadr6 0bh eadr7 0ch rxflush 0dh ? 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh ? ? ? ? ? ? ? ? ? ? ? ? txnmtrig ? ? ? ? ? 20h ? 21h ? 22h ? 23h txsr 24h ? 25h ? 26h ? 27h ? 28h ? 29h ? 2ah ? 2bh ? 2ch ? 2dh ? 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh ? ? isrsts intmsk gpio trisgpio ? rfctl ? ? ? bbreg2 ? ? ? bbreg6 rssithcca rfctrl0 200h ? 201h rfctrl2 202h rfctrl3 203h ? 204h ? 205h rfctrl6 206h rfctrl7 207h rfctrl8 208h ? 209h ? 20ah ? 20bh ? 20ch ? 20dh ? 20eh 20fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21ah 21bh 21ch 21dh 21eh 21fh ? ? clkintcr ? ? ? ? ? ? ? ? ? ? ? ? ? ? clkctrl 220h ? 221h ? 222h ? 223h ? 224h ? 225h ? 226h ? 227h ? 228h ? 229h 22ah ? 22bh ? 22ch ? 22dh ? 22eh 22fh 230h 231h 232h 233h 234h 235h 236h 237h 238h 239h 23ah 23bh 23ch 23dh 23eh 23fh ? ? ? ? ? ? ? ? ? ? 240h 241h ? 242h ? 243h ? 244h ? 245h ? 246h ? 247h ? 248h ? 249h ? 24ah ? 24bh ? 24ch ? ? ? ? ? ? ? ? ? ?
? 2006 microchip technology inc. advance information ds39776a-page 11 mrf24j40 3.2 mrf24j40 address summary table 3-1: register file short address summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por details on page: rxmcr txcrcen bblpbk acken maclpbk pancoord coord rxcrcen promi 0000 0000 21 panidl mac pan low byte (panl<7:0>) 0000 0000 26 panidh mac pan high byte (panh<15:8>) 0000 0000 26 sadrl mac short address low byte (saddrl<7:0>) 0000 0000 27 sadrh mac short address high byte (saddrh<15:8>) 0000 0000 27 eadr0 lsb of eui (eadr0<7:0>) 0000 0000 26 eadr1 byte 2 of eui (eadr1<15:8>) 0000 0000 26 eadr2 byte 3 of eui (eadr2<23:16>) 0000 0000 26 eadr3 byte 4 of eui (eadr3<31:24>) 0000 0000 26 eadr4 byte 5 of eui (eadr4<39:32>) 0000 0000 26 eadr5 byte 6 of eui (eadr5<47:40>) 0000 0000 26 eadr6 byte 7 of eui (eadr6<55:48>) 0000 0000 26 eadr7 msb of eui (eadr7<63:56>) 0000 0000 26 rxflush ? r r rxwrtblk cmdonly dataonly bcnonly rxflush -000 0000 34 txnmtrig ? ? ? pendack indirect ackreq secen txrts ---0 0000 30 txsr txretry<7:6> ccafail r r r r r 0000 0000 31 isrsts slpif wakeif hsymtmrif secif rxif gts2txif gts1txif txif 0000 0000 36 intmsk slpmsk wakemsk hsymtmrmsk secmsk rxmsk gts2txmsk gts1txmsk txmsk 1111 1111 37 gpio ? ? gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 --00 0000 39 trisgpio ? ? trisgp5 trisgp4 trisgp3 trisgp2 trisgp1 trisgp0 --00 0000 40 rfctl r ? ?rrrfrstrr 0--0 0000 24 bbreg2 ccamode<7:6> ccathres<5:2> ? ? 0000 00-- 25 bbreg6 rssireq rxrssi r r r r r rssirdy 0000 0001 25 rssithcca rssithres<7:0> 0000 0000 23 legend: - = unimplemented, r = reserved. shaded cells are unimplemented, read as ? 0 ?. table 3-2: register file long address summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por details on page: rfctrl0 channel<7:4> ? ? ? ? 0000 ---- 24 rfctrl2 rfpll r r r r ? ? ? 0000 0--- 22 rfctrl3 txpower<7:3> ? ? ? 0000 0--- 22 rfctrl6 txfil ?r rbatmonen ? ? ? 0-00 0--- 23 rfctrl7 slpclk<7:6> ? ? ? ? clkdiv<1:0> 00-- --00 8 rfctrl8 ? ? ?rf_vco ? ? ? slpclkout ---0 ---0 23 clkintcr ? ? ? ? ? ? intedge slpclken ---- --00 38 clkctrl r ?clkoen sclkdiv<4:0> 0-00 0000 7 legend: - = unimplemented, r = reserved. shaded cells are unimplemented, read as ? 0 ?.
mrf24j40 ds39776a-page 12 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 13 mrf24j40 4.0 serial peripheral interface (spi) 4.1 overview the mrf24j40 is designed to interface directly with the serial peripheral interface (spi) port available on many microcontrollers. the implementation used on this device supports spi mode 0,0 only. in addition, the spi port requires that sck be idle in a low state; selectable clock polarity is not supported. commands and data are sent to the device via the sdi pin, with data being clocked in on the rising edge of sck. data is driven out by the mrf24j40 on the sdo line, on the falling edge of sck. the cs pin must be held low while any operation is performed and returned high when finished. the mrf24j40 accesses the short and long ram banks in a slightly different manner. the following sections describe the required waveforms in order to read and write from both short and long ram addresses. figure 4-1: spi input timing figure 4-2: spi output timing cs sck sdi sdo lsb in msb in high-impedance state cs sck sdo msb out lsb out don?t care sdi
mrf24j40 ds39776a-page 14 advance information ? 2006 microchip technology inc. 4.2 short address register interface 4.2.1 reading short address registers the short address space is accessed by sending a ? 0 ? as the first bit of the spi transfer. the following 6 bits are the address of the target register. the final bit of the first byte is a ? 0 ? to indicate that the command is a read. on the next clock edge of sck, the most significant bit of the register will shift out, followed by the rest of the bits. figure 4-3: short address read example 4-1: short address read example sck sdi sdo cs a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x 00 byte getshortramaddress(byte address) { byte toreturn; csn = 0; spiput((address<<1)&0b01111110); toreturn = spiget(); csn = 1; return toreturn; }
? 2006 microchip technology inc. advance information ds39776a-page 15 mrf24j40 4.2.2 writing short address registers the short address space is accessed by sending a ? 0 ? as the first bit of the spi transfer. the following 6 bits are the address of the target register. the final bit of the first byte is a ? 1 ? to indicate that the command is a write. on the next clock edge of sck, the most significant bit of the register will shift out, followed by the rest of the bits. figure 4-4: short address write example 4-2: short address write example sck sdi sdo cs a5 a4 a3 a2 a1 a0 x 0 1 d7 d6 d5 d4 d3 d2 d1 d0 void setshortramaddress(byte address, byte value) { csn = 0; spiput(((address<<1)&0b01111111)|0x01); spiput(value); csn = 1; }
mrf24j40 ds39776a-page 16 advance information ? 2006 microchip technology inc. 4.3 long address register interface 4.3.1 reading long address registers the long address space is accessed by sending a ? 1 ? as the first bit of the spi transfer. the following 10 bits are the address of the target register. the final bit is a ? 0 ? to indicate that the command is a read. on the next clock edge of sck, the most significant bit of the register will shift out, followed by the rest of the bits. figure 4-5: long address read example 4-3: long address read example sck sdi sdo cs a9 a8 a7 a6 a5 d7 d6 d5 d4 d3 d2 d1 d0 x a4 a3 a2 a1 a0 0 x 1 byte getlongramaddress(word address) { byte toreturn; csn = 0; spiput(((address>>3)&0b01111111)|0x80); spiput(((address<<5)&0b11100000)); toreturn = spiget(); csn = 1; return toreturn; }
? 2006 microchip technology inc. advance information ds39776a-page 17 mrf24j40 4.3.2 writing long address registers the long address space is accessed by sending a ? 1 ? as the first bit of the spi transfer. the following 10 bits are the address of the target register. the final bit is a ? 1 ? to indicate that the command is a write. on the next clock edge of sck, the most significant bit of the register will shift out, followed by the rest of the bits. 4.4 buffer interface the receive and transmit buffers in the mrf24j40 are located in the long ram address space. these buffers are accessed using the same process as accessing the long ram control addresses. the received buffer is read-only and should not be written to. the use of these buffers is described in section 7.0 ?transmitting and receiving packets? . figure 4-6: long address write example 4-4: long address write example sck sdi sdo cs a9 a8 a7 a6 a5 d7 d6 d5 d4 d3 d2 d1 d0 x a4 a3 a2 a1 a0 1 x 1 void setlongramaddress(word address, byte value) { csn = 0; spiput((((byte)(address>>3))&0b01111111)|0x80); spiput((((byte)(address<<5))&0b11100000)|0x10); spiput(value); csn = 1; }
mrf24j40 ds39776a-page 18 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 19 mrf24j40 5.0 ieee 802.15.4?-2003 5.1 overview before discussing the use of the mrf24j40, it may be helpful to review the structure of a typical data frame. users requiring more information should refer to the ieee 802.15.4 standard. 5.2 packet format normal ieee 802.15.4 compliant packets are between 5 and 127 bytes long. they are made up of several possi- ble fields: destination address information, source address information, a length field, data payload and a cyclic redundancy check (crc). additionally, a 4-byte preamble field and start-of-frame delimiter (sfd) byte are appended to the beginning of the packet. thus, traffic seen on the air will appear as shown in figure 5-1. figure 5-1: packet format number of bytes 4 preamble field comments sfd 1 packet length 1 frame control 2 destination address information 0/4/10 source address information 0/2/4/8/ 10 sequence number 1 data payload 0-122 fcs 2 frame check sequence ? crc used to fcs filtered out by module start-of-frame delimiter ? filtered out by module short or long address of the destination device plus the pan identifier. length selected in the frame control. short or long address of the source device plus the pan identifier. length selected in the frame control. used to calculate packet length calculate
mrf24j40 ds39776a-page 20 advance information ? 2006 microchip technology inc. 5.2.1 preamble/start-of-frame delimiter when transmitting and receiving data with the mrf24j40, the preamble and start-of-frame delimiter bytes will automatically be generated or stripped from the packets when they are transmitted or received. the host controller does not need to concern itself with them. normally, the host controller will also not need to concern itself with the crc, which the mrf24j40 will also be able to automatically generate when transmit- ting and verify when receiving. the crc fields will, however, be written into the receive buffer when packets arrive, so they may be evaluated by the host controller if needed. 5.2.2 length the length field is a 1-byte field which defines the size of the packet excluding itself, the preamble and sfd, but including all other bytes of the packet, including fcs. 5.2.3 frame control the frame control field describes the format of this packet. it defines the type of packet (beacon, data, ack, etc.) the addressing modes used, if the packet is encrypted or not, if the packet requires an ack and if the packet is an intra-pan network. this information is used by the host controller to determine how to decipher the data that follows the frame control field. 5.2.4 sequence number the sequence number field is a 1-byte sequence number that distinguishes packets. the sequence number field is used in the acknowledgement process. an ack packet contains no addressing information, so the uniqueness of the sequence number is the sole determining factor for verifying that a packet reached its destination. the mrf24j40 has an auto-acknowledgement feature that is described in section 7.1 ?transmitting packets? . 5.2.5 destination address information the destination address fields of an ieee 802.15.4 packet can change depending on the frame control field of that packet. the frame control field can specify that no destination address is present, or can specify that the short address (2 bytes) or long address (8 bytes) is present. in all cases where an address is specified, the destination pan identifier will also be included. on incoming packets, the mrf24j40 will filter out packets that do not match the preconfigured addressing information for that radio. this eliminates any software intervention for packets that do not meet the addressing requirements. when transmitting the host controller is required to write the appropriate destination address into the transmit buffer. 5.2.6 source address information the source address fields of an ieee 802.15.4 packet can change depending on the frame control field of that packet. the frame control field can specify that no destination address is present, or can specify that the short address (2 bytes) or long address (8 bytes) is present. the frame control can also specify, by using the intra-pan bit, that the source pan matches the destination pan and is thus, not included in the packet. long addresses consist of two portions. the first three bytes are known as the extended organizationally unique identifier (eui). euis are distributed by the ieee 802.15.4. the last five bytes are address bytes which can contain the needed requirements at the discretion of the company that purchased the eui. when transmitting packets, the assigned source long or short address, depending on the setting of the frame control field, must be written into the transmit buffer by the host controller. the mrf24j40 will not automatically include the source address information. 5.2.7 data the data section of the packet can vary in length from 0 bytes to 122 bytes. packets that exceed 127 bytes, including the frame control, source addressing, desti- nation addressing, data and fcs fields, will be filtered out by the mrf24j40. 5.2.8 fcs the fcs field is a 2-byte field which contains an industry standard, 16-bit crc calculated with the data from the frame control, sequence number, destination, source, and data fields. when receiving packets, the mrf24j40 will check the crc of each incoming packet. if the rx crcen bit (rxmcr<1>) is cleared, packets with invalid crcs will automatically be dis- carded. if rx crcen is set, and the packet meets all other receive filtering criteria, the packet will be written into the receive buffer and the host controller will be able to determine if the crc was valid by reading the receive status vector (see section 7.3 ?receiving packets? ). when transmitting packets, the mrf24j40 will auto- matically generate a valid crc and transmit it attached to the end of the packet if the txcrcen bit (rxmcr<7>) is cleared.
? 2006 microchip technology inc. advance information ds39776a-page 21 mrf24j40 6.0 initialization 6.1 overview before the mrf24j40 can be used to transmit and receive packets, certain device settings must be initial- ized. depending on the application, some configuration options may need to be changed. normally, these tasks may be accomplished once after reset and do not need to be changed thereafter. 6.2 receive filters to minimize the processing requirements of the host controller, the mrf24j40 incorporates several different receive filters which can automatically reject packets which are not needed. these options are controlled through the rxmcr register. register 6-1: rxmcr: receive filter control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 txcrcen r acken r pancoord coord rxcrcen promi bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 txcrcen : no crc data with normal fifo bit 1 = crc is disabled for the tx fifo 0 = crc is enabled for the tx fifo bit 6 reserved: maintain as ? 0 ? bit 5 acken: no ack respond in any case bit 1 = ack response is always disabled 0 = ack response enabled. acks are returned when they are requested. bit 4 reserved: maintain as ? 0 ? bit 3 pancoord: pan coordinator bit 1 = set as pan coordinator 0 = not set as pan coordinator bit 2 coord: coordinator bit 1 = set as coordinator 0 = not set as coordinator bit 1 rxcrcen : error report bit 1 = rx all kinds of pkt (including crc error) 0 = only rx pkt (crc ok) bit 0 promi: rx all kinds of pkt bit (crc ok) 1 = rx all kinds of pkt (crc ok) 0 = discard pkt when there is a mac address mismatch, illegal frame type, dpan/span or mac short address mismatch
mrf24j40 ds39776a-page 22 advance information ? 2006 microchip technology inc. 6.3 phy initialization the physical layer of the mrf24j40 controls the current levels going to different sections of the device, as well as thresholds and controls used in packet reception and transmission. there are several registers that may require modification in order to operate in the application?s intended mode. note: the rssi threshold defaults to ? 0 ?, how- ever, it can be set to a user-defined rssi threshold limit. please note, any rssi value resulting from a cca request that is below the rssi threshold limit will result in a failure. register 6-2: rfctrl2: rf control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 rfpll (1) rrrr ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rfpll: rf-pll control bit (1) 1 = pll enabled 0 = pll disabled bit 6-3 reserved: maintain as ? 0 ? bit 2-0 unimplemented: read as ? 0 ? note 1: pll must be enabled for rf reception or transmission. register 6-3: rfctrl3: rf control register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 txpower<7:3> ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 txpower7:txpower3: small scale control for tx power in db bits 00000 = 0 db 00001 = -1.25 db 00010 = -2.5 db 00011 = -3.75 db 00100 = -5 db 00101 = -6.25 db 00110 = -7.5 db 00111 = -8.75 db ? 11111 = -38.75 db bit 2-0 unimplemented: read as ? 0 ?
? 2006 microchip technology inc. advance information ds39776a-page 23 mrf24j40 register 6-4: rfctrl6: rf control register 6 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 txfil ?rr batmonen ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 txfil: tx filter control bit recommended value: ? 1 ?. bit 6 unimplemented: read as ? 0 ? bit 5-4 reserved: maintain as ? 0 ? bit 3 batmonen: battery monitor enable bit 1 = enabled 0 = disabled bit 2-0 unimplemented: read as ? 0 ? register 6-5: rfctrl8: rf control register 8 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 ? ? ? rf_vco ? ? ? slpclkout bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 rf_vco: vco control bit 1 = enhanced vco (recommended) 0 = normal vco bit 3-1 unimplemented: read as ? 0 ? bit 0 slpclkout: 20 mhz reference output clock source bit 1 = stabilize clkout while recovering from sleep 0 = stabilize clkout after a wake from sleep register 6-6: rssithcca: rssi threshold for cca register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rssithres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 rssithres7:rssithres0: rssi threshold for cca/ed mode bits
mrf24j40 ds39776a-page 24 advance information ? 2006 microchip technology inc. 6.4 mac initialization the medium access control layer of the mrf24j40 consists of several registers that define how this device operates on an ieee 802.15.4 network. 6.4.1 device configuration the rxmcr, described in section 6.2 ?receive filters? , should be set to the appropriate value for the intended device operation. if the device is operating as a pan coordinator, the pancoord bit should be set. if the device is operating as a coordinator, then the coord bit should be set. 6.4.2 channel selection the operational channel is selected using the rfctrl0 register. register 6-7: rfctrl0: rf control register 0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 channel<7:4> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 channel7:channel4: channel number bits 00000 = channel 11 00001 = channel 12 00010 = channel 13 ? 11111 = channel 26 bit 3-0 unimplemented: read as ? 0 ? register 6-8: rfctl: rf mode control register w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r ? ?r r rfrst rr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 reserved: maintain as ? 0 ? bit 6-5 unimplemented: read as ? 0 ? bit 4-3 reserved: maintain as ? 0 ? bit 2 rfrst: rf reset bit 1 = reset rf (turn off rf) 0 = normal operation bit 1-0 reserved: maintain as ? 0 ?
? 2006 microchip technology inc. advance information ds39776a-page 25 mrf24j40 register 6-9: bbreg2: baseband cca/rssi mode register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ccamode<7:6> ccathres<5:2> ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 ccamode7:ccamode6: cca mode bits 00 =reserved 01 = cca mode 1, carrier sense only 10 = cca mode 2, energy above threshold 11 = cca mode 3, carrier sense with energy above threshold bit 5-2 ccathres5:ccathres2: cca carrier sense threshold bits cca/cs value set to 0xe or ? 1110 ?. bit 1-0 unimplemented: read as ? 0 ? register 6-10: bbreg6: baseband rssi mode register 6 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 rssireq rxrssi rr r r r rssirdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rssireq: rssi mode 1 bit 1 = initiate an rssi calculation (write back to ? 0 ? when complete) 0 = otherwise bit 6 rxrssi: rssi mode 2 bit 1 = calculating rssi for rx packet 0 = no calculating rssi for rx packet bit 5-1 reserved: maintain as ? 0 ? bit 0 rssirdy: rssi ready signal firmware request bit 1 = rssi value ready 0 = otherwise
mrf24j40 ds39776a-page 26 advance information ? 2006 microchip technology inc. 6.4.3 long addresses every device in the world has a unique long address. long addresses are described in more detail in section 5.2.5 ?destination address information? and section 5.2.6 ?source address information? . eadr0-eadr7 are eight short ram address registers in the mrf24j40 that are used to define the device?s long address. these addresses should be loaded into the device during the device configuration. the mrf24j40 will automatically filter out any long address packets that do not match the contents of eadr0-eadr7. 6.4.4 short address and pan id the device?s short address and pan id are programmed into the mrf24j40 through the sadrl, sadrh, panidl and panidh register s. these registers are located in the short ram address space. the mrf24j40 automatically filters out packets that are specified as short address destinations with addresses that do not match these registers. the exception to this rule is packets with the broadcast short address (ffffh) and/or the broadcast pan id (ffffh). packets that match the short address and have the broadcast pan id will be accepted, as well as packets with the broadcast short address that match the pan id. a true broadcast packet will have both the short address and pan id set to the broadcast address. the mrf24j40 will also receive these packets no matter what the setting of the short address and pan id registers. example 6-1 shows how to initialize the mrf24j40. register 6-11: panidl: mac pan low byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mac pan low byte (panl<7:0>) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 panl7:panl0: lower byte of pan address bits register 6-12: panidh: mac pan high byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mac pan high byte (panh<15:8>) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 panh15:panh8: higher byte of pan address bits
? 2006 microchip technology inc. advance information ds39776a-page 27 mrf24j40 register 6-13: sadrl: mac short address low byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mac short address low byte (saddrl<7:0>) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 saddrl7:saddrl0: lower byte of short address bits register 6-14: sadrh: mac short address high byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mac short address high byte (saddrh<15:8>) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 saddrh15:saddrh8: higher byte of short address bits
mrf24j40 ds39776a-page 28 advance information ? 2006 microchip technology inc. example 6-1: initializing the mrf24j40 void mrf24j40init(void) { byte i; word j; /* place the device in hardware reset */ resetn = 0; for(j=0;j<(word)300;j++){} /* remove the device from hardware reset */ resetn = 1; for(j=0;j<(word)300;j++){} /* reset the rf module */ setshortramaddr(rfctl,0x04); /* remove the rf module from reset */ setshortramaddr(rfctl,0x00); /* flush the rx fifo */ setshortramaddr(write_rxflush,0x01); /* program the short mac address, 0xffff */ setshortramaddr(sadrl,0xff); setshortramaddr(sadrh,0xff); setshortramaddr(panidl,0xff); setshortramaddr(panidh,0xff); /* program long mac address*/ for(i=0;i<(byte)8;i++) { setshortramaddr(eadr0+i*2,mylongaddress[i]); } /* enable the rf-pll */ setlongramaddr(rfctrl2,0x80); /* set tx for max output power */ setlongramaddr(rfctrl3,0x00); /* enabled tx filter control */ setlongramaddr(rfctrl6,0x80); setlongramaddr(rfctrl8,0b00010000); /* program cca mode using rssi */ setshortramaddr(bbreg2,0x78); /* enable the packet rssi */ setshortramaddr(bbreg6,0x40); /* program cca, rssi threshold values */ setshortramaddr(rssithcca,0x00); setlongramaddr(rfctrl0,0x00); //channel 11 setshortramaddr(rfctl,0x04); //reset the rf module with new settings setshortramaddr(rfctl,0x00); }
? 2006 microchip technology inc. advance information ds39776a-page 29 mrf24j40 7.0 transmitting and receiving packets 7.1 transmitting packets the mac inside the mrf24j40 will automatically generate the preamble and start-of-frame delimiter fields when transmitting. additionally, the mac can generate any padding (if needed), and the crc, if configured to do so. the host controller must generate and write all other frame fields into the buffer memory for transmission. before transmitting packets, the mac registers, which alter the transmission characteristics, should be initialized as documented in section 6.0 ?initialization? . 7.2 tx fifo format the tx mac performs three major tasks conforming to ieee 802.15.4: ? tx fifo control ? automatic csma-ca and timing alignments ? hardware superframe handling for tx fifo control function, tx mac controls 4 fifos, including beacon, normal and 2 gts fifos. when each fifo is triggered, tx mac performs a csma-ca algorithm, sends a packet to the transmit baseband (txbb) at the right time, handles the retransmission if an ack is required but not received and generates fcs bytes automatically. the automatic csma-ca algorithm performs timing alignments, such as lifs, sifs and ack turnaround time. the user can simply program parameters for the csma-ca algorithm. the tx mac will perform automatically according these parameters. for hardware superframe handling, tx mac builds up the timing frame of a superframe. it includes cap, cfp, inactive and each time slot. tx mac sends beacon, normal and gts fifos at the right time, automatically, at each transmission. this largely reduces the complexity of the beacon enable mode of ieee 802.15.4. figure 7-1: transmit packet layout address header length memory description packet length (m + 3) frame control sequence number data[0] data[m ? 1] length of the header. this field is described in more detail in the security section of this document. the length of the packet, not including the length or fcs. the destination and source addressing information, as well as any application data. data[...] 0x000 0x001 0x002-0x003 0x004 0x005 the frame control field describing how this packet should behave. the sequence number distinguishing this packet. fcs[1] fcs[0] the crc value for the packet; written by hardware. 0x005 + (m ? 1) 0x006 + m 0x007 + m
mrf24j40 ds39776a-page 30 advance information ? 2006 microchip technology inc. 7.2.1 trigger packet transmission the mrf24j40 handles the clear channel assess- ment (cca) and carrier sense multiple access colli- sion avoidance (csma-ca) algorithms in hardware. the mrf24j40 also handles automatic retransmission of packets that require an ack. if the frame control field of the packet requires an ack, the ackreq bit (txnmtrig<2>) needs to be set before transmission. once the tx fifo is loaded with the data to transmit the txrts bit (txnmtrig<0>) is used to transmit the packet. register 7-1: txnmtrig: trigger and setting for normal frame (cap) register u-0 u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 w-0 ? ? ? pendack indirect (1) ackreq (1) secen (1) txrts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 pendack: data pending status in ack bit status of the data pending bit in ack from previous transmission. this bit is reset by hardware on the next transmission. 1 = data pending bit was set 0 = data pending bit was cleared bit 3 indirect: activate indirect transmission bit (1) 1 = indirect transmission enabled 0 = indirect transmission disabled bit 2 ackreq: tx packet in txn fifo needs ack response bit (1) 1 = ack requested 0 = no ack requested bit 1 secen: secure current tx packet bit (1) 1 = secure packet 0 = send packet without securing it bit 0 txrts: trigger tx mac to send the packet in tx fifo bit 1 = send the packet in the tx fifo, automatically cleared by hardware note 1: this bit is cleared at the next triggering of txn fifo.
? 2006 microchip technology inc. advance information ds39776a-page 31 mrf24j40 7.2.2 transmission status when a transmission completes, the txif flag of the isrsts register will become set. once the txif bit is set, the status of the transmission is located in the txsr register. 7.3 receiving packets the following section details the reception of a non-secured frame. when the mrf24j40 receives a packet that passes the mac layer addressing, thresh- old and packet type filters, it will indicate the reception of this packet to the host controller by setting the rxif bit (isrsts<3>). the packet will remain in the buffer until the host frees the buffer. no other packets can be received while the buffer is holding a packet. 7.4 rx mac the rx mac block will do crc checking, parse the received frame type and address recognition, then store the received frame into rx fifo. in addition to the ieee 802.15.4 packet, there are also 2 bytes of information that are appended to the end of the packet after the fcs field: lqi and rssi. the behavior of rx fifo follows a certain rule. when a received packet is not filtered or dropped, a received interrupt/status will be issued. the interrupt is read-to-clear to save host operation time. however, the rx fifo is flushed only using the following three methods: ? the host reads the first byte and the last byte to the packet ? the host issues rx flush ? a software is reset for rx filter function, the promiscuous mode is supported to receive all fcs-ok packets. an error mode is supported to receive all packets that successfully correlated phy level preamble and delimiter. register 7-2: txsr: tx mac status register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 txretry<7:6> ccafail rrrrr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 txretry7:txretry6: retry times bits defines the retry times of the most recent txn fifo transmission. bit 5 ccafail: clear channel assessment (cca) status of last transmission bit 1 = cca failed 0 = cca passed bit 4-0 reserved: maintain as ? 0 ?
mrf24j40 ds39776a-page 32 advance information ? 2006 microchip technology inc. figure 7-2: receive process packet received rxif = 1 rxmcr.rxcrcen n = 1 ? accept packet crc valid? no no rxmcr.promi = 1 ? yes yes long address destination? no no no matches eadr0- eadr7? yes no matches sadrh, sadrl, panidh, panidl or 0xffff? yes no data packet? beacon packet? command packet? rxflush.data only = 1 ? rxflush.bcn only = 1 ? rxflush.cmd only = 1 ? yes yes yes no no no yes yes no no yes reject packet reject packet reject packet reject packet yes reject packet reject packet accept packet accept packet over the air, no yes yes short address destination?
? 2006 microchip technology inc. advance information ds39776a-page 33 mrf24j40 7.4.1 receive packet layout when a packet passes all of the enabled filters, it is placed in the receive fifo in the following format. figure 7-3: receive packet layout . address memory description packet length (m + 5) frame control sequence number data[0] data[m ? 1] the length of the packet, not including the packet length, but does include the fcs. the destination and source addressing information as well as any application data. data[...] 0x300 0x301-0x302 0x303 0x304 the frame control field describing how this packet should behave. the sequence number distinguishing this packet. fcs[1] fcs[0] the crc value for the packet; written by hardware. 0x304 + (m ? 1) 0x305 + m 0x306 + m lqi 0x307 + m rssi 0x308 + m the link quality index of the received packet. the received signal strength indicator for the received packet.
mrf24j40 ds39776a-page 34 advance information ? 2006 microchip technology inc. 7.4.2 freeing receive buffer space the rx buffer is cleared when the length byte of the packet and the last byte of the fcs are read. once both of these values are read from the rx buffer, the buffer will enable itself to receive another packet. because the lqi and rssi values are appended to the end of the packet after the fcs, it may be advisable to read these values out of the rx buffer before reading the fcs. alternatively, it is possible to clear the rx buffer by flushing it. this is done through the rxflush register. 7.5 transceiver the mrf24j40 receiver features a low if architecture and consists of an lna, a pair of down conversion mixers, polyphase channel filters, baseband limiter amplifiers and rssi technology. an adc is used to sample the rssi value and the sampled data is stored in a register from which the data can be read out via the spi bus. the local oscillator generation circuits (vco, pll and buffers) are shared with the receiver and transmitter. the low noise amplifier (lna) features a differential input for high performance. the rx/tx switch is integrated and lna input and power amplifier (pa) output share the same pins. a common external matching network and single-ended to differential con- version is required. the transmitter features a direct conversion architecture and has a 0 to -38.75 dbm out- put power. the output power adjustment is in 1.25 db step. the tx gain is programmed by the spi bus. register 7-3: rxflush: receive fifo flush register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 w-0 ? rrrxwrtblk cmdonly dataonly bcnonly rxflush bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-5 reserved: maintain as ? 0 ? bit 4 rxwrtblk : software write to rx fifo address bit 1 = writing to any rx fifo address is enabled 0 = writing to any rx fifo address is disabled bit 3 cmdonly: command packet receive bit 1 = only command packets are received, all other packets are filtered out 0 = all valid packets are received bit 2 dataonly: data packet receive bit 1 = only data packets are received, all other packets are filtered out 0 = all valid packets are received bit 1 bcnonly: beacon packet receive bit 1 = only beacon packets are received, all other packets are filtered out 0 = all valid packets are received bit 0 rxflush: flush rx fifo address bit 1 = flush the rx fifo. cleared by hardware. 0 = previous flush complete
? 2006 microchip technology inc. advance information ds39776a-page 35 mrf24j40 8.0 interrupts the mrf24j40 has a simple interrupt structure. there is one interrupt pin that signals all of the possible events. the isrsts register is a read-to-clear register that specifies which interrupt(s) caused the interrupt. the intmsk register is used to block unwanted inter- rupt sources from generating interrupts. the intedge bit (clkintcr<1>) controls the polarity of the interrupt pin. once isrsts is read by the host controller, the interrupt flags are cleared. the host controller should make certain to handle all returned flags each time the isrsts register is read. 8.1 interrupt structure when an enabled interrupt occurs, the interrupt pin will remain at its interrupt state, as determined by the intedge bit, until all of the flags which are causing the interrupt are cleared or masked off (the mask bits are set) by the host controller. if more than one interrupt source is enabled, the host controller must poll each flag in the isrsts register to determine the source(s) of the interrupt. figure 8-1: mrf24j40 interrupt logic intmsk.slpmsk isrsts.slpif intmsk.wakemsk isrsts.wakeif intmsk.hsymtmrmsk isrsts.hsymtmrif intmsk.secmsk isrsts.secif intmsk.rxmsk isrsts.rxif intmsk.gts2txmsk isrsts.gts2txif intmsk.gts1txmsk isrsts.gts1txif intmsk.txmsk isrsts.txif int clkintcr.intedge
mrf24j40 ds39776a-page 36 advance information ? 2006 microchip technology inc. 8.1.1 int interrupt status registers the registers associated with the int interrupts are shown in register 8-1, register 8-2 and register 8-3. register 8-1: isrsts: interrupt status register rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 slpif wakeif hsymtmrif secif rxif gts2txif gts1txif txif bit 7 bit 0 legend: rc = read to clear r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 slpif: sleep alert interrupt bit 1 = sleep alert interrupt occurred 0 = otherwise bit 6 wakeif: wake-up alert interrupt bit 1 = wake-up interrupt occurred 0 = otherwise bit 5 hsymtmrif: half symbol timer interrupt bit 1 = half symbol timer interrupt occurred 0 = otherwise bit 4 secif: security key request interrupt bit 1 = security key request interrupt occurred 0 = otherwise bit 3 rxif: rx ok interrupt bit 1 = rx ok interrupt occurred 0 = otherwise bit 2 gts2txif: gts fifo 2 release interrupt bit 1 = gts2 transmission interrupt occurred 0 = otherwise bit 1 gts1txif: gts fifo 1 release interrupt bit 1 = gts1 transmission interrupt occurred 0 = otherwise bit 0 txif: tx fifo release interrupt bit 1 = tx fifo transmission interrupt occurred 0 = otherwise
? 2006 microchip technology inc. advance information ds39776a-page 37 mrf24j40 register 8-2: intmsk: interrupt mask register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 slpmsk wakemsk hsymtmrmsk secmsk rxmsk gts2txmsk gts1txmsk txmsk bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 slpmsk: sleep alert mask bit 0 = enable sleep interrupt 1 = otherwise bit 6 wakemsk: wake-up alert mask bit 0 = enable wake interrupt 1 = otherwise bit 5 hsymtmrmsk: half symbol timer mask bit 0 = enable half symbol timer interrupt 1 = otherwise bit 4 secmsk: security interrupt mask bit 0 = enable security interrupt 1 = otherwise bit 3 rxmsk: rx ok mask bit 0 = enable receive interrupt 1 = otherwise bit 2 gts2txmsk: gts fifo 2 irq mask bit 0 = enable gts fifo 2 transmit interrupt 1 = otherwise bit 1 gts1txmsk: gts fifo 1 irq mask bit 0 = enable gts fifo 1 transmit interrupt 1 = otherwise bit 0 txmsk: tx normal fifo irq mask bit 0 = enable normal fifo transmit interrupt 1 = otherwise
mrf24j40 ds39776a-page 38 advance information ? 2006 microchip technology inc. register 8-3: clkintcr: slpclk on/off and interrupt polarity register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? intedge slpclken bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 intedge: interrupt edge polarity bit 1 = rising edge 0 = falling edge bit 0 slpclken : sleep clock enable bit 1 = disabled 0 = enabled
? 2006 microchip technology inc. advance information ds39776a-page 39 mrf24j40 9.0 general purpose i/o 9.1 gpio registers the mrf24j40 has 6 available, general purpose i/o pins. these pins are interfaced through the gpio and trisgpio registers. example 9-1: read/write example register 9-1: gpio: gpio port register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 gpio5: general purpose i/o gpio5 bit bit 4 gpio4: general purpose i/o gpio4 bit bit 3 gpio3: general purpose i/o gpio3 bit bit 2 gpio2: general purpose i/o gpio2 bit bit 1 gpio1: general purpose i/o gpio1 bit bit 0 gpio0: general purpose i/o gpio0 bit setshortaddress(trisgpio,0x03); //set gpio5-2 to output, and gpio 1-0 as input setshortaddress(gpio,0x01); //set gpio0 high and gpio1 as low.
mrf24j40 ds39776a-page 40 advance information ? 2006 microchip technology inc. register 9-2: trisgpio: gpio pin direction and spi mode register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? trisgp5 trisgp4 trisgp3 trisgp2 trisgp1 trisgp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 trisgp5: general purpose i/o gpio5 direction bit 1 =output 0 = input bit 4 trisgp4: general purpose i/o gpio4 direction bit 1 =output 0 = input bit 3 trisgp3: general purpose i/o gpio3 direction bit 1 =output 0 = input bit 2 trisgp2: general purpose i/o gpio2 direction bit 1 =output 0 = input bit 1 trisgp1: general purpose i/o gpio1 direction bit 1 =output 0 = input bit 0 trisgp0: general purpose i/o gpio0 direction bit 1 =output 0 = input
? 2006 microchip technology inc. advance information ds39776a-page 41 mrf24j40 10.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............. -40c to +85c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any combined digital and analog pin with respect to v ss (except v dd )........................ -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3v to 3.6v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum output current sunk by gpio1-gpio5 pins ................................................................................ ..............1 ma maximum output current sourced by gpio1-gpio5 pins ............................................................................. ............1 ma maximum output current sunk by gpio0 pin ....................................................................................... .....................4 ma maximum output current sourced by gpio0 pin .................................................................................... ...................4 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mrf24j40 ds39776a-page 42 advance information ? 2006 microchip technology inc. table 10-1: recommended operating conditions table 10-2: current consumption typical values: t a = 25c, v dd = 3.3v table 10-3: receiver ac characteristics typical values: t a = 25c, v dd = 3.3v, lo frequency = 2.445 ghz parameters min typ max units ambient operating temperature -40 ? +85 c supply voltage for rf, analog and digital circuits 2.4 ? 3.6 v supply voltage for digital i/o 2.4 3.3 3.6 v input high voltage (v ih ) 0.5 x v dd ?v dd + 0.3 v input low voltage (v il ) -0.3 ? 0.2 x v dd v chip mode condition min typ max units sleep ? 2 tbd a tx at maximum output power ? 22 tbd ma rx ? 18 tbd ma legend: tbd = to be determined parameters condition min typ max units rf input frequency 2.4 ? 2.483 ghz rf sensitivity at antenna input with o-qpsk signal and 3.5 db front end loss is assumed ?-91?dbm maximum rf input lna at high gain +5 ? ? dbm lo leakage measured at balun matching network input at frequency 2.405-2.48 ghz ?-60?dbm input return loss externally matched to 50 source by a balun matching network -12 -20 ? db noise figure (including matching) ?8?db adjacent channel rejection @ +/- 5 mhz 30 ? ? db alternate channel rejection @ +/- 10 mhz 40 ? ? db rssi range ? 50 ? db rssi error -5 ? 5 db
? 2006 microchip technology inc. advance information ds39776a-page 43 mrf24j40 table 10-4: transmitter ac characteristics typical values: t a = 25c, v dd = 3.3v, lo frequency = 2.445 ghz figure 10-1: example spi slave mode timing table 10-5: example spi slave mode requirements parameters condition min typ max units rf carrier frequency 2.4 ? 2.483 ghz maximum rf output power ? 0 ? dbm rf output power control range ? 38.75 ? db tx gain control resolution programmed by register ? 1.25 ? db carrier suppression ? -30 ? dbc tx spectrum mask for o-qpsk signal offset frequency > 3.5 mhz, at 0 dbm output power -33 ? ? dbm tx evm ? ? 25 % tx noise floor ? ? -126 dbm/hz param no. symbol characteristic min max units conditions 70 t ss l2 sc hcs to sck input 50 ? ns 71 t sc h sck input high time single byte 50 ? ns 72 t sc l sck input low time single byte 50 ? ns 74 t sc h2 di l hold time of sdi data input to sck edge 25 ? ns 75 t do r sdo data output rise time ? 25 ns 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge tbd ? ns 82 t ss l2 do v sdo data output valid after cs edge tbd ? ns 83 t sc l2 ss hcs after sck edge 50 ? ns legend: tbd = to be determined cs sck sdo 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 msb in bit 6 - - - - 1 lsb in 80 83 70
mrf24j40 ds39776a-page 44 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 45 mrf24j40 11.0 packaging information 11.1 package marking information xxxxxxxxxx 40-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn mrf24j40 example -i/mm 0610017 legend: xx...x product-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e
mrf24j40 ds39776a-page 46 advance information ? 2006 microchip technology inc. 11.2 package details the following sections give the technical details of the packages. 40-lead plastic quad flat, no lead package (mm) 6x6x0.9 mm body [qfn] with 0.40 mm contact length note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging numb e r of pins pitch ov e rall h e ight standoff contact thickn e ss ov e rall width expos e d pad width ov e rall l e ngth expos e d pad l e ngth contact width contact l e ngth contact-to-expos e d pad units dim e nsion limits n e a a1 a 3 e e2 d d2 b l k 0.80 0.00 4.00 4.00 0.18 0. 3 0 0.20 40 0.50 bsc 0.90 0.02 0.20 ref 6.00 bsc 4. 3 7 6.00 bsc 4. 3 7 0.25 0.40 ? 1.00 0.05 4.75 4.75 0. 3 0 0.50 ? min nom max millimeters notes: 1. pin 1 visual ind e x f e atur e may vary, but must b e locat e d within th e hatch e d ar e a. 2. significant charact e ristic 3 . packag e is saw singulat e d 4. dim e nsioning and tol e rancing p e r asme y14.5m bsc: basic dim e nsion. th e or e tically e xact valu e shown without tol e ranc e s. ref: r e f e r e nc e dim e nsion, usually without tol e ranc e , for information purpos e s only. microchip t e chnology drawing no. c04?118, 09/15/06 bottom view top view d exposed pad d2 e e2 note 1 a 3 a1 a 1 2 1 2 n n l k b e
? 2006 microchip technology inc. advance information ds39776a-page 47 mrf24j40 appendix a: layout and part selection a.1 layout considerations and rf measurements below is an example of the circuit diagram of a balun. a balun is the impedance transformer from unbalanced input of the pcb antenna and the balanced input of the rf transceiver (pins rfp and rfn). figure a-2 shows the measured impedance of the balun where the center of the band is very close to 50 . when using low tolerance components (i.e., 5%) along with an appropriate ground, the impedance will remain close to the 50 measurement. figure a-3 shows the measured impedance of the pcb antenna using a logarithmic scale magnitude. figure a-4 shows the same impedance using a smith chart diagram and figure a-5 using a voltage standing wave ratio. figure a-1: example circuit diagram figure a-2: measured impedance ant 0.3 pf ?gnd l1 4.7 nh 0.5 pf c38 0.5 pf l3 5.6 nh c43 0.5 pf c40 100 nf 0.5 pf rfp rfn 10 nh 10 nh c7 c23 l4 c37 l5
mrf24j40 ds39776a-page 48 advance information ? 2006 microchip technology inc. figure a-3: impedance of the pcb antenna figure a-4: impedance of the pcb antenna in smith chart
? 2006 microchip technology inc. advance information ds39776a-page 49 mrf24j40 figure a-5: impedance of the pcb antenna with voltage standing wave ratio the most critical part of maintaining proper impedance is adhering to the specified dimensions of the printed circuit board antenna (see figure a-6). the antenna dimensions, if altered, will change the specified imped- ance. as an example, a 1 mm variance will shift the impedance by 5-10 mhz. figure a-6: printed circuit board antenna dimensions note: this part has been simulated using a hfss? simulator provided by ansoft corporation. 1.0 1.0 1.0 1.0 1.0 0.72 3.37 0.85 0.5 3.82 4.2 6.6 4.3 1.2 1.3 2 . 0 3.8 5.3 8.6 22.0 1.2 6.0 1.54 0.5
mrf24j40 ds39776a-page 50 advance information ? 2006 microchip technology inc. figure a-7 and figure a-8 illustrate simulation results of this pcb antenna. note the simulation results are very close to the measurements. figure a-7: simulated pcb antenna impedance, xy plot
? 2006 microchip technology inc. advance information ds39776a-page 51 mrf24j40 figure a-8: simulated pcb antenna impedance, smith plot
mrf24j40 ds39776a-page 52 advance information ? 2006 microchip technology inc. a.2 pcb layout design the following guidelines are intended to aid users who are not experienced in high-frequency pcb layout design. the printed circuit board is comprised of four basic fr4 layers: signal layout, rf ground, power line routing and ground (see figure a-9). the guidelines will explain the requirements of these layers. figure a-9: four basic copper fr4 layers ? it is important to keep the original pcb thickness since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines characteristic impedance. ? the first layer width of a 50 characteristic impedance microstrip line is 12 mils. ? avoid having microstrip lines longer than 2.5 cm, since that line might get very close to a quarter wave length of the working frequency of the board which is 3.0 cm, and start behaving as an antenna. ? except for the antenna layout, avoid sharp corners since they can act as an antenna. round corners will eliminate possible future emi problems. ? digital lines by definition are prone to be very noisy when handling periodic waveforms and fast clock/switching rates. avoid laying out a rf signal close to any digital lines. ? a via filled ground patch underneath the ic transceiver is mandatory. ? a power supply must be distributed to each pin in a star topology and low-esr capacitors must be placed at each pin for proper decoupling noise. ? decoupling each power pin is a tedious task, especially when the noise is affecting the perfor- mance of the transceiver in a specific bandwidth. usually, low value caps (15-27 pf) combined with large value caps (100 nf) will cover a large spectrum of frequency. ? passive components (inductors) must be in the high-frequency category and the srf (self- resonant frequency) should be at least two times higher than the operating frequency. figure a-10 and figure a-11 illustrate the ground and power plane for the rf board. dielectric = 4.5, thickness = 7 mils signal layout, thickness = 1.8 mils rf ground, thickness = 1.2 mils dielectric = 4.5, thickness = 19 mils power line routing, thickness = 1.2 mils dielectric = 4.5, thickness = 7 mils ground, thickness = 1.8 mils note: care should be taken with all ground lines to prevent breakage.
? 2006 microchip technology inc. advance information ds39776a-page 53 mrf24j40 figure a-10: ground plane figure a-11: power ground plane m antenna note: see figure a-6 for antenna dimensions
mrf24j40 ds39776a-page 54 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 55 mrf24j40 appendix b: mrf24j40 schema tic and bill of materials b.1 schematic figure b-1: mrf24j40 schematic ant c7 0.3 pf c38 +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v nl 32.768 khz nl c64 y1 c60 nl c63 10 nf +3.3v c55 27 pf 27 pf c58 c54 20 pf 20 mhz y3 c21 20 pf c52 10 nf c53 2.2 f c19 27 pf r20 0 l5 10 nh 180 pf c48 c40 47 pf 100 nf c39 0.5 pf c37 l3 5.6 nh 0.5 pf l4 10 nh c44 27 pf c45 r19 10k +3.3v c43 0.5 pf mrf24j40 1 2 3 4 5 6 7 8 9 10 v dd _rf1_3v rfp rfn v dd v dd gnd gpio0 gpio1 gpio5 gpio4 gpio2 gpio3 reset gnd 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 int sdo sdi sck cs wake rxqp rxip lposc2 clkout gnd gnd nc gnd v dd lposc1 40 39 38 37 36 35 34 33 32 31 v dd v dd osc2 osc1 gnd v dd nc v dd lcap v dd pic ? microcontroller gpio spi module rb0/int osc1 ?gnd gpio l1 4.7 nh c23 0.5 pf 100 nf optional note: center pad on qfn package must be grounded.
mrf24j40 ds39776a-page 56 advance information ? 2006 microchip technology inc. b.2 bill of materials table b-1: mrf24j40 daughter card bill of materials quantity component name reference description value description vendor vendor # 1 cap3528 c1 2.2 f_tant capacitor tant, 2.2 f, 25v, 10%, smd kemet t491b225k025at 4 cap0402 c23, c37, c38, c43 0.5 pf cap, ceramic, 0.5 pf, 50v, np0, 0402 yageo america 0402cg508c9b200 2 cap0402 c21, c54 20 pf cap, ceramic, 20 pf, 50v, 5%, c0g, 0402 murata electronics grm1555c1h200jz01d 4 cap0402 c19, c44, c55, c58 27 pf cap, ceramic, 27 pf, 50v, 0402, smd panasonic - ecg ecj-0ec1h270j 1 cap0402 c40 47 pf cap, ceramic, 47 pf, 50v, c0g, 5%, 0402 tdk corporation c1005c0g1h470j 2 cap0402 c52, c63 10 nf cap, ceramic, 10000 pf, 16v, x7r, 0402 kemet c0402c103k4ractu 2 cap0402 c39, c45 100 nf c0402c104k8pactu kemet c0402c104k8pactu 1 cap0402 c48 180 pf cap, ceramic, 180 pf, 50v, c0g, 5%, 0402 tdk corporation c1005c0g1h181j 1 cap0603 c53 2.2 f cap, ceramic, 2.2 f, 10v, y5v, 0603 taiyo yuden lmk107f225za-t 1 crystal_abm8 y3 20 mhz crystal, 20.000 mhz, 18 pf, fund, smd abracon corporation abm8-20.000mhz-b2-t 1 mrf24j40_qlp40 u1 mrf24j40, single chip transceiver microchip mrf24j40-i/ml 1 ind0402 l1 4.7 nh inductor multilayer, 4.7 nh, 0402 tdk corporation mlk1005s4n7s 1 ind0402 l3 5.6 nh inductor multilayer, 5.6 nh, 0402 tdk corporation mlk1005s5n6d 2 ind0402 l4, l5 10 nh inductor multilayer, 10 nh, 0402 tdk corporation mlk1005s10nj 2 res0402 r20, r22 0 res, 0 , 1/16w, 5%, 0402, smd panasonic - ecg erj-2ge0r00x 1 res0402 r19 10k res, 10 k , 1/16w, 5%, 0402, smd yageo america rc0402jr-0710kl 1 hdr6x2 j2 .100" socket/terminal samtec lst-106-07-f-d
? 2006 microchip technology inc. advance information ds39776a-page 57 mrf24j40 b.3 revision history revision a (december 2006) original data sheet for the mrf24j40 device.
mrf24j40 ds39776a-page 58 advance information ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. advance information ds39776a-page 59 mrf24j40 index a absolute maximum ratings ................................................41 ac characteristics receiver .....................................................................42 transmitter .................................................................43 b bill of materials ...................................................................56 block diagrams example circuit ..........................................................47 interrupt logic .............................................................35 mrf24j40 architecture ................................................4 packet format ............................................................19 buffer interface ...................................................................17 c cca clear channel assessment ........................................30 channel selection ..............................................................24 code examples gpio read/write ........................................................39 initializing the mrf24j40 ...........................................28 long address read ....................................................16 long address write ....................................................17 short address read ...................................................14 short address write ...................................................15 control registers long address ...............................................................9 mapping, long address ..............................................10 mapping, short address .............................................10 short address ...............................................................9 coord bit .........................................................................24 csma-ca ...........................................................................29 carrier sense multiple access collision avoidance ............................................30 current consumption .....................................................3, 42 customer change notification service ...............................61 customer notification service ............................................61 customer support ..............................................................61 d device configuration ..........................................................24 device overview ...................................................................3 features (40-pin devices) ............................................3 differential rf pin negative rfn ......................................................................8 positive rfp ......................................................................8 e electrical characteristics ....................................................41 errata ....................................................................................2 example spi slave mode requirements ...........................43 extended organizationally unique identifier (eui) .............20 external connections ...........................................................7 clkout pin .................................................................7 oscillator .......................................................................7 start-up .................................................................7 g general purpose i/o .......................................................... 39 gpio registers trisgpio gpio pin direction and spi mode register ..................................... 40 i ieee 802.15.4 ......................................................................3 ieee 802.15.4-2003 ........................................................... 19 impedance measured ................................................................... 47 pcb antenna ............................................................. 48 pcb antenna in smith chart ...................................... 48 pcb antenna with voltage standing wave ratio ........................................................ 49 simulated pcb antenna, smith plot ..........................51 simulated pcb antenna, xy plot .............................. 50 initialization ........................................................................ 21 integrated oscillator drive .................................................... 3 internet address ................................................................. 61 interrupts ............................................................................ 35 structure ..................................................................... 35 l layout considerations ....................................................... 47 long address register interface ........................................ 16 reading ......................................................................16 writing ........................................................................ 17 long address summary ..................................................... 11 long addresses ................................................................. 26 m mac initialization ............................................................... 24 memory organization ........................................................... 9 microchip internet web site ...............................................61 p packages ............................................................................. 3 packaging .......................................................................... 45 details ........................................................................ 46 marking ......................................................................45 packet format ....................................................................19 cyclic redundancy check (crc) .. ............................ 19 data field ................................................................... 20 data payload .............................................................. 19 destination address ................................................... 19 destination address fields ........................................ 20 fcs field ................................................................... 20 frame control field ................................................... 20 frame delimiter .......................................................... 20 length field ......................................................... 19, 20 sequence number field ............................................ 20 source address .......................................................... 19 source address fields ...............................................20 pan id ............................................................................... 26 pancoord bit ................................................................. 24 pcb ground plane ............................................................. 53 layout design ............................................................ 52 power ground plane .................................................. 53
mrf24j40 ds39776a-page 60 advance information ? 2006 microchip technology inc. pcb antenna dimensions ................................................................ 49 simulation results ..................................................... 50 phy initialization ................................................................ 22 pin descriptions ................................................................... 5 clkout (clock output) .............................................. 5 cs (serial interface enable) ........................................ 5 gnd (ground, digital circuit) ...................................... 5 gnd (ground, pll) ..................................................... 5 gnd (guard ring ground) .......................................... 5 gpio0 (external pa enable) ....................................... 5 gpio1 (external tx/rx switch control) ...................... 5 gpio2 (external tx/rx switch control) ...................... 5 gpio3 (general purpose digital i/o) ........................... 5 gpio4 (general purpose digital i/o) ........................... 5 gpio5 (general purpose digital i/o) ........................... 5 int (interrupt pin) ........................................................ 5 lcap (pll loop filter external capacitor) ................. 5 lposc1 (32 khz crystal input) ................................... 5 lposc2 (32 khz crystal input) ................................... 5 nc (no connection) ..................................................... 5 osc1 (20 mhz crystal input) ...................................... 5 osc2 (20 mhz crystal input) ...................................... 5 reset (global hardware reset active-low) .............. 5 rfn (differential rf pin, negative) ............................. 5 rfp (differential rf pin, positive) ............................... 5 rxip (analog rx i channel output) ............................ 5 rxqp (analog rx q channel output) ........................ 5 sck (serial interface clock) ........................................ 5 sdi (serial interface data input) .................................. 5 sdo (serial interface data output) ............................. 5 v dd (charge pump power supply) .............................. 5 v dd (digital circuit power supply) ............................... 5 v dd (guard ring power supply) .................................. 5 v dd (pll power supply) .............................................. 5 v dd (power supply, analog circuit) ............................. 5 v dd (power supply, band gap reference circuit) ................................................ 5 v dd (rf power supply) ............................................... 5 v dd (vco supply) ....................................................... 5 wake (external wake-up trigger) .............................. 5 power-saving mode ............................................................. 3 proprietary protocols ............................................................ 1 miwi ............................................................................. 1 zigbee ...................................................................... 1, 9 r reader response .............................................................. 62 receive buffers .................................................................... 9 receive filters ................................................................... 21 receive packets ................................................................ 21 receive process flowchart ................................................ 32 receiving packets .............................................................. 31 freeing buffer space ................................................. 34 layout ........................................................................ 33 recommended operating conditions ................................ 42 reference clock output ....................................................... 3 register file summary ....................................................... 11 registers bbreg2 (baseband cca/rssi mode 2) .................. 25 bbreg6 (baseband rssi mode 6) .......................... 25 clkctrl (divided sleep clock selection) ................. 7 clkintcr (slpclk on/off and interrupt polarity) ............................................... 38 gpio (gpio port) ...................................................... 39 intmsk (interrupt mask) ........................................... 37 isrsts (interrupt status) .......................................... 36 panidh (mac pan high byte) ................................. 26 panidl (mac pan low byte) .................................. 26 rfctl (rf mode control) ........................................ 24 rfctrl0 (rf control 0) ........................................... 24 rfctrl2 (rf control 2) ........................................... 22 rfctrl3 (rf control 3) ........................................... 22 rfctrl6 (rf control 6) ........................................... 23 rfctrl7 (rf control 7) ............................................. 8 rfctrl8 (rf control 8) ........................................... 23 rssithcca (rssi threshold for cca) ................... 23 rxflush (receive fifo flush) ............................... 34 rxmcr (receive filter control) ................................ 21 sadrh (mac short address high byte) .................. 27 sadrl (mac short address low byte) .................... 27 trisgpio (gpio pin direction and spi mode) ................................................... 40 txnmtrig (trigger and setting for normal frame, cap) .................................... 30 txsr (tx mac status) ............................................. 31 rf measurements ............................................................. 47 rf output ............................................................................ 8 rf transceiver .................................................................. 47 rssi default threshold ..................................................... 22 rx fifo ............................................................................. 31 rx mac ............................................................................. 31 s schematic .......................................................................... 55 security buffer ..................................................................... 9 serial communications ........................................................ 3 serial peripheral interface (spi) ........................................ 13 short address register interface ....................................... 14 reading ..................................................................... 14 writing ....................................................................... 15 short address summary .................................................... 11 short addresses ................................................................ 26 sleep mode .......................................................................... 3 t timing diagrams example spi slave mode .......................................... 43 long address read ................................................... 16 long address write ................................................... 17 short address read .................................................. 14 short address write ................................................... 15 spi input .................................................................... 13 spi output ................................................................. 13 transmit buffers .................................................................. 9 transmit packets ............................................................... 21 transmitting packets ......................................................... 29 status ........................................................................ 31 trigger packet ........................................................... 30 tx fifo ............................................................................. 30 tx fifo format ................................................................. 29 tx mac ............................................................................. 29 w www address .................................................................. 61 www, on-line support ................... ................................... 2 z zigbee v1.0 specification .................................................... 9
? 2006 microchip technology inc. advance information ds39776a-page 61 mrf24j40 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
mrf24j40 ds39776a-page 62 advance information ? 2006 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39776a mrf24j40 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2006 microchip technology inc. advance information ds39776a-page 63 mrf24j40 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device mrf24j40: ieee 802.15.4? 2.4 ghz rf transceiver temperature range i = -40 c to +85 c (industrial) package mm = qfn (plastic quad flat, no lead) example: a) mrf24j40-i/mm: industrial temperature, qfn package.
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